- Verification Methodology Manual for Low Power [Purchase hard copy]
- Verification Methodology Manual for Low Power [Download PDF]
- Low Power Methodology Manual
- IC Design and Verification Journal: You Really Verified Your Multi-rail, Low Power Design?
- Low Power Design Portal: Experts from the VMM for Low Power
- Chip Design: Experts at the Table: Low-Power Management and Verification
- Chip Design: Verifying Low-Power Designs
- EE Times: Why voltage-aware verification strategy counts
- Chip Design: Moore's Law vs. Low Power
- New Electronics: Low power verification methodology: Is this a case of natural evolution?
- EDACafe: Power and Verification Always Matter [A review of the VMM-LP book]
- EDN: Chip-verification and -design flow focus on low power
- EDN: Verification methodology for low power: Your blueprint to working silicon
- EE Times: Boost verification accuracy with low-power assertions
- Chip Design: A Ticking Time Bomb?
- Chip Design: Coding Practices Adapt to a Low-Power World