Author Bios
SRIKANTH JADCHERLAGroup Director of R&D, Verification Group Synopsys, Inc. Srikanth Jadcherla came to Synopsys as part of the ArchPro acquisition, where he was founder and CTO. Prior to ArchPro, Jadcherla was an IC designer and architect at companies such as WSI, Intel, Jasmine and Synopsys. He is a veteran of low power designs and pioneer of many energy efficiency techniques and principles. Jadcherla received an Intel Achievement Award for his work on low power and is the author of 12 patents. He is an honorary green evangelist/technical advisor to various companies ranging from solar energy suppliers to real estate developers. Recently, he has been advocating new paradigms in energy efficient design in semiconductor systems worldwide from both the supply and demand side of energy consumption. Mr. Jadcherla holds a Bachelor's Degree in Electrical Engineering from IITMadras in India, and a Master's Degree in Computational Science and Engineering from the University of California, Santa Barbara. |
JANICK BERGERONSynopsys Fellow Synopsys, Inc. Janick Bergeron is a Fellow at Synopsys Inc. responsible for the development and specification of the functional verification methodology to be supported by their digital simulation products. He is the author of the best-selling "Verification Methodology Manual for SystemVerilog" and of the "Writing Testbenches" book series. Both are the first industry references on modern functional verification techniques and methodologies. Mr. Bergeron holds a Bachelors Degree in Engineering from the Universite du Quebec a Chicoutimi, a Master of Applied Sciences in Electrical Engineering from the University of Waterloo VLSI program, and an MBA from the University of Oregon through the Oregon Executive MBA program. |
YOSHIO INOUEChief Engineer Renesas Technology Corp. Yoshio Inoue is Chief Engineer of Design Technology Div. at Renesas Technology Corp., which was formed through the merger of semiconductor operations of Hitachi and Mitsubishi on April 1st, 2003. He holds a Bachelor of Science Degree at Tokyo Denki University. He joined Mitsubishi Electric as a gate array design engineer in 1984. Since 1989 he has been involved in advanced EDA design methodology development and EDA design systems to support the US's high-speed, high-complexity SoC designs. When Renesas was formed, he focused more on RTL prototyping technology for Japanese and US customers' designs. He has expanded his area of focus to ultra low power design methodology such as application processors for cellular phones and is a pioneer in the area of hierarchical power management. |
DAVID FLYNNARM R&D Fellow Visiting Professor, Southampton University David Flynn, a Fellow in R&D at ARM Ltd., has been with the company since 1991, specializing in System-on-Chip IP deployment and methodology. He is the original architect behind ARM's synthesizable CPU family and the AMBA on-chip interconnect standard. His current research focus is low-power system-level design. He holds a number of patents in on-chip buses, low -power and embedded processing sub-system design and holds a Bachelor of Science Degree in Computer Science from Hatfield Polytechnic, UK and a Doctorate in Electronic Engineering from Loughborough University, UK. He is currently Visiting Professor with the Electronics and Computer Science Department at Southampton University, UK. |
